Many digital signal processing applications, such as radio base stations or VDSL modems, require A/D converters with very high sample rate and very high accuracy. To achieve high enough sample rates, an array of M A/D converters or ADCs, interleaved in time, can be used. Each ADC should work at 1/M th of the desired sample rate [7], see FIG. 1. In FIG. 1 a parallel ADC system is shown consisting of a plurality of single or individual ADCs 1, even called ADC cells or ADC channels, which convert successively sampled values in a cyclical process, the conversion in each cell is performed in parallel with the conversion in the other cells. The conversion process in each cell starts at successive times for successively sampled analog values. An analog signal u(t) is input to the device on a line 2. A sampling clock signal is input to control terminals of the ADC cells on a line 3 and is successively delayed by delay elements 4 connected to the clock input line. The signals provided to the control terminals command the start of the conversion procedure in the respective ADC cell. The M output signals from the ADC cells, y1 to yM, are connected to a MUX 5. The MUX puts the signals y1 to yM together to form one output signal y. The delay elements and input circuits of the ADC cells cause time offset errors.
Three kinds of mismatch errors are introduced by the interleaved structure:
Time Errors or Static Jitter:
The delay time of the clock to the different A/D converters is not equal. This means that the signal will be periodically but non-uniformly sampled.
Amplitude Offset Errors:
The ground level can be slightly different in the different A/D converters. This means that there is constant amplitude offset in each A/D converter.
Gain Error:
The gain, from analog input to digital output, can be different for the different A/D converters.
The errors listed above are assumed to be static, so that the error is the same in the same A/D converter from one cycle to the next. There are also random errors due to for instance thermal noise and quantization, which are different from one sample to the next. These errors do not have anything to do with the parallel structure of the A/D converter and are impossible to estimate because of their random behavior. The random errors are however important to study for the robustness of the estimation algorithm and to calculate lower bounds on the estimation accuracy.
The main random errors in an A/D converter are:
Quantization:
This is a deterministic error, if the input signal is known. But for most signals it can be treated as additive white noise uncorrelated with the input signal and with uniform distribution [11].
Random Jitter:
Due to noise in the clock signal there is a random error on the sampling instances. These errors can be treated as Gaussian white noise on the sampling instances.